A problem which plagues semiconductor memory devices is that of parasitic leakage. In NMOS devices, for example, parasitic leakage occurs between N-doped regions of neighboring memory cells. Parasitic leakage in such devices is caused by the formation of an undesired channel beneath the insulating field oxide separating the neighboring memory cells. More specifically, parasitic leakage occurs at and along the edges of row or word lines arranged on top of the field oxide. Electrons from the N-doped regions of a memory cell migrate beneath the field oxide at and along the edges of a word lines to a neighboring memory cell when a sufficiently high voltage is applied to that word line.
Typically, the parasitic leakage problem has been obviated through the use of a thick and long field channel insulating field oxide. Unfortunately, this technique is not conducive to a goal of scaling down memory device size to increase memory density. As processing technology improves, memory devices are being scaled down below 0.5 micron. As these devices are scaled down to such sizes, thick and long field channel insulating field oxides can no longer be formed.
Accordingly, as processes improve, the problem of parasitic leakage returns.
Parasitic leakage is not as severe a problem in memory devices having low word line and digit line voltages, such as 5 volts. However, as the digit line and word line voltages are increased to levels such as 10-15 volts or more, the problem becomes more severe. For this reason, the problem of parasitic leakage is particularly relevant for electrically programmable read only memories (EPROMs) and electrically erasable programmable read only memories (EEPROMs). EPROM and EEPROM cells can be programmed after manufacture by applying high voltages to selected memory cells to electrically bias the memory cells and create binary "1"'s and "0"'s. The high voltages are applied to digit lines and word lines used to access the selected memory cell. Parasitic leakage occurs during the programming of the individual EPROM and EEPROM cells as a result of the high voltages being applied to the digit and word lines. Such leakage is detrimental to the programmability of the memory.
The present invention provides a semiconductor memory device which reduces parasitic leakage between neighboring memory cells.